NXP Semiconductors jobs
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Principal Analog IP Design Lead - MCU
NXP Semiconductors - CataniaIndexed from Workday Benefit evidence checked May 7, 2026posted 77 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"+1
Unspecified Design From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Analog IP Design Lead - MCU Catania posted: Posted 9 Days Ago
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Director – Export Control and Sanctions Compliance
NXP Semiconductors - Austin (Oakhill, Office)Indexed from Workday Benefit evidence checked May 7, 2026posted 97 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"+1
Unspecified Finance From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedDirector – Export Control and Sanctions Compliance Austin (Oakhill, Office) posted: Posted 29 Days Ago
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Chandler Fab Office Manager
NXP Semiconductors - Chandler (Office)Indexed from Workday Benefit evidence checked May 7, 2026posted 89 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"Unspecified Other - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedChandler Fab Office Manager Chandler (Office) posted: Posted 21 Days Ago
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Principal Engineer, ASIC Development Engineering (Mixed-Signal IP Layout)
SanDisk - Bengaluru, KA, IndiaIndexed from Smartrecruitersposted 70 days agoWhy we showed this
Role: semantic matchUnspecified Engineering From the posting source - Principal From the posting source Salary not disclosed EquityPrincipal Engineer, ASIC Development Engineering (Mixed-Signal IP Layout) Bengaluru, KA, India Company Description: Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description: We are looking for technically sound and highly skilled Analog/High Speed DDR IO Layout designer with 8-12 years of experience. The ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize MSIP IC layouts in TSMC 3nm, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements
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Films Equipment Engineer - Novellus C2
NXP Semiconductors - Austin (Ed Bluestein, Office)Indexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedFilms Equipment Engineer - Novellus C2 Austin (Ed Bluestein, Office) posted: Posted 30+ Days Ago
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Senior Accountant & SOX Specialist
NXP Semiconductors - Kuala LumpurIndexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"Unspecified Finance From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Accountant & SOX Specialist Kuala Lumpur posted: Posted 30+ Days Ago
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ASIC Engineering Analog Design Leader | high-speed optical transceiver circuits (modulator drivers, TIAs, CDRs, PLLs, ADC/DAC) | 12+ years, Bangalore
Cisco - Bangalore, IndiaIndexed from Workday Benefit evidence checked Jun 13, 2026posted 68 days agoWhy we showed this
Role: semantic matchApply link reachable when checkedUnspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedASIC Engineering Analog Design Leader | high-speed optical transceiver circuits (modulator drivers, TIAs, CDRs, PLLs, ADC/DAC) | 12+ years, Bangalore Bangalore, India Cisco's Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG's ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry. You will work with Cisco's best-in-class Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures. We seek an experienced High Speed AMS Design Engineer to lead full-chip electrical specifications and mixed-signal design for Cisco's silicon photonics driver integrated circuits supporting 100G/200G/400G per Lambda solutions. You will own high-speed datapath and low-speed control circuit design for receive and transmit paths in our next-generation silicon photonics modules. Your Impact As a High-Speed Analog/Mixed-Signal (AMS) Design Leader, you will play a pivotal role in shaping next-generation silicon photonics driver ICs. You will: Lead full-chip electrical architecture, specifications, and execution for high-speed silicon photonics driver
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Device Engineer (Einfochips Inc)
Arrow Electronics - Peachtree City, Georgia, United States of AmericaIndexed from Phenom People Benefit evidence checked Jun 7, 2026posted 113 days agoWhy we showed this
Role: semantic matchUnspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedDevice Engineer (Einfochips Inc) Peachtree City, Georgia, United States of America Embrace the role of a Device Engineer and drive innovation in automotive software solutions. Collaborate with cross-functional teams, design secure Android and Linux platforms, and ensure seamless integration of vehicle systems. Shape the future of automotive technology with eInfochips and make a real impact on next-generation mobility solutions.
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Electrical Engineer FPGA/ASIC - Level 3/4 - Dulles
Northrop Grumman Corporation - United States-Virginia-DullesIndexed from Eightfold Benefit evidence checked Jun 7, 2026posted 68 days agoWhy we showed this
Role: semantic matchUnspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedElectrical Engineer FPGA/ASIC - Level 3/4 - Dulles United States-Virginia-Dulles
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NNTE - Optical Engineer
Vodafone Group - Athens, Attiki, GreeceIndexed from Eightfold Benefit evidence checked Jun 7, 2026posted 68 days agoWhy we showed this
Role: semantic matchUnspecified Data From the posting source - Mid From the posting source Salary not disclosed Inferred from posting 401(k) reportedNNTE - Optical Engineer Athens, Attiki, Greece
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Systems and Control Engineer, High Tech Utilities
NXP Semiconductors - NijmegenIndexed from Workday Benefit evidence checked May 7, 2026posted 69 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSystems and Control Engineer, High Tech Utilities Nijmegen posted: Posted Yesterday
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System IC Architect - Advanced Power Systems
NXP Semiconductors - 3 LocationsIndexed from Workday Benefit evidence checked May 7, 2026posted 75 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSystem IC Architect - Advanced Power Systems 3 Locations posted: Posted 7 Days Ago
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Key Account Manager - Automotive
NXP Semiconductors - Shanghai (JingAn)Indexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"Unspecified Trades From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedKey Account Manager - Automotive Shanghai (JingAn) posted: Posted 30+ Days Ago
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Wire Bond Shift Assistant Engineer
NXP Semiconductors - KaohsiungIndexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedWire Bond Shift Assistant Engineer Kaohsiung posted: Posted 30+ Days Ago
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Hardware Design Engineer(Einfochips Inc.)
Arrow Financial CORP - US-MA-Bedford-Massachusetts (Werfen)Indexed from Workday Comp disclosed in postingposted 99 days agoWhy we showed this
Role: semantic matchApply link reachable when checkedUnspecified Engineering From the posting source - Mid From the posting source $135K-$145K From the posting source Inferred from posting Learning budget Equity Unknown provenance 401(k) reportedHardware Design Engineer(Einfochips Inc.) US-MA-Bedford-Massachusetts (Werfen) Position: Hardware Design Engineer(Einfochips Inc.) Job Description: What candidate will Be Doing: Drive and contribute to all stages of the Hardware Product Development Lifecycle, from concept to production. Design and develop hardware architectures based on microcontrollers including ST, Microchip, and Texas Instruments (TI). Create analog and mixed-signal circuit designs including ADC/DAC, signal conditioning, and discrete analog components. Design and validate AC-DC and DC-DC power supply circuits to meet system requirements. Work on signal integrity and noise management using operational amplifiers and discrete components. Develop and implement communication interfaces such as RS232, RS485, I2C, SPI, UART; exposure to wireless protocols (Wi-Fi, Bluetooth, Zigbee) is a plus. Ensure compliance with Electromagnetic Interference (EMI) and Electromagnetic Compatibility (EMC) standards, especially for automotive-grade products. Utilize EDA tools like OrCAD, Allegro, Altium, and PADS for schematic and PCB design. Perform debugging, validation, and bring-up of hardware prototypes using lab equipment such as multimeters, oscilloscopes, function generators, and logic analyzers. Collaborate cross-functionally with firmware, mechanical, and test engineering teams to ensure design robustness and manufacturability. What we are looking for: Experience of atleast 5 years in all stages of Hardware Product Development Lifecycle. Microcontroller: ST, Microchip, TI, based architecture design Analog and mixed signal design, ADC and DAC circuit design experience, Signal conditioning Operational amplifier, discrete component analog circuit design experience AC to DC and DC to DC power supply design Knowledge of interfaces like RS232, RS485, I2C, SPI, UART, Wi-Fi, BT, Zigbee would be plus. Electromagnetic Interference (EMI) /
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Die Attach Equipment Technician
NXP Semiconductors - Kuala LumpurIndexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedDie Attach Equipment Technician Kuala Lumpur posted: Posted 30+ Days Ago
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Lead Software Engineer – AI Operators
NXP Semiconductors - HyderabadIndexed from Workday Benefit evidence checked May 7, 2026posted 71 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedLead Software Engineer – AI Operators Hyderabad posted: Posted 3 Days Ago
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2026 Campus - SoC Backend Design Engineer
NXP Semiconductors - Tianjin (Teda)Indexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reported2026 Campus - SoC Backend Design Engineer Tianjin (Teda) posted: Posted 30+ Days Ago
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Senior Software Application Engineer – Ethernet Products (f/m/d)
NXP Semiconductors - HamburgIndexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"+1
Unspecified Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Software Application Engineer – Ethernet Products (f/m/d) Hamburg posted: Posted 30+ Days Ago
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N1 Metrology Equipment Technician
NXP Semiconductors - Austin (Ed Bluestein, Manufacturing)Indexed from Workday Benefit evidence checked May 7, 2026posted 71 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedN1 Metrology Equipment Technician Austin (Ed Bluestein, Manufacturing) posted: Posted 3 Days Ago
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Project Manager AAES Tools Team
NXP Semiconductors - BucharestIndexed from Workday Benefit evidence checked May 7, 2026posted 70 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"Unspecified Marketing From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedProject Manager AAES Tools Team Bucharest posted: Posted 2 Days Ago
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Trade Compliance Operations Coordinator
NXP Semiconductors - Kuala LumpurIndexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"Unspecified Finance From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedTrade Compliance Operations Coordinator Kuala Lumpur posted: Posted 30+ Days Ago
- posted 118 days ago
Why we showed this
Role: semantic matchPCB Layout Engineer (Taiwan) Taipei, Taiwan About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We're seeking a skilled PCB Layout Engineer to join our dynamic team and contribute to our high-performance data center products. As a PCB Layout Engineer at Etched, you will play a crucial role in designing and optimizing printed circuit boards (PCBs) using Cadence Allegro PCB design tools. Your primary focus will be on high-speed signaling, including 100G applications, power distribution, large BGA ball-map breakouts and complex HDI PCB stack-ups for high-performance data center products. Your expertise will ensure that our products meet the highest standards of performance, reliability, and efficiency. Key Responsibilities - Lead the design and optimization of high-speed PCB layouts using Cadence Allegro, tailored for 100G signaling. Implement strategies for impedance matching, trace routing, and crosstalk mitigation, resulting in robust designs that meet the stringent performance demands of modern data centers. - Develop and implement power distribution networks for cutting-edge data center hardware. Design power planes, decoupling strategies, and thermal management solutions to support high-performance systems, ensuring reliability and
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Audio Algorithm Engineer F/M
NXP Semiconductors - Sophia-Antipolis (Valbonne)Indexed from Workday Benefit evidence checked May 7, 2026posted 76 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedAudio Algorithm Engineer F/M Sophia-Antipolis (Valbonne) posted: Posted 8 Days Ago
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