Intel jobs
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Senior GenAI Software Architect
Intel - 2 LocationsIndexed from Workday Benefit evidence checked Jun 13, 2026posted 143 days agoWhy we showed this
Employer: "intel"Unspecified Engineering From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedSenior GenAI Software Architect 2 Locations posted: Posted 30+ Days Ago
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Senior Physical Design Engineer
Intel - India, BangaloreIndexed from Workday Benefit evidence checked Jun 13, 2026posted 123 days agoWhy we showed this
Employer: "intel"Unspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Physical Design Engineer India, Bangalore posted: Posted 11 Days Ago
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Advanced Technology: AI/ML Research Scientist
Cerebras Systems - Sunnyvale, CA; Toronto, Ontario, Canada; Vancouver, British Columbia, CanadaIndexed from Greenhouse Benefit evidence checked Jun 7, 2026posted 178 days agoWhy we showed this
Description: "intel"Role: semantic matchUnspecified Data From the posting source - Mid From the posting source Salary not disclosed Inferred from posting 401(k) reportedAdvanced Technology: AI/ML Research Scientist Sunnyvale, CA; Toronto, Ontario, Canada; Vancouver, British Columbia, Canada Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. About The Team Cerebras builds wafer-scale AI processors-single chips delivering tens of PB/s of memory bandwidth and a dataflow architecture that accelerates at a granularity no multi-device system can match. The Advanced Technology Group (ATG) is Cerebras ' pathfinding organization. We work ahead of product to explore new architectures, demonstrate breakthrough performance on scientific and AI workloads, and shape the technical roadmap for future Cerebras hardware and software. Our work regularly appears at top-tier venues (Supercomputing, SIAM, IEEE,
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SoC Physical Design Engineer
Intel - India, BangaloreIndexed from Workday Benefit evidence checked Jun 13, 2026posted 119 days agoWhy we showed this
Employer: "intel"Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedSoC Physical Design Engineer India, Bangalore posted: Posted 7 Days Ago
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Temporary Change Management Practitioner
Intel - 4 LocationsIndexed from Workday Benefit evidence checked Jun 13, 2026posted 114 days agoWhy we showed this
Employer: "intel"Unspecified Finance From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedTemporary Change Management Practitioner 4 Locations posted: Posted 2 Days Ago
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Member of Technical Staff - Compute Infrastructure
xAI - Palo Alto, CA; Seattle, WAIndexed from Greenhouse Comp disclosed in postingposted 209 days agoWhy we showed this
Role: semantic matchUnspecified Engineering From the posting source - Staff Plus From the posting source $180K-$440K From the posting source EquityMember of Technical Staff - Compute Infrastructure Palo Alto, CA; Seattle, WA ABOUT xAI xAI's mission is to create AI systems that can accurately understand the universe and aid humanity in its pursuit of knowledge. Our team is small, highly motivated, and focused on engineering excellence. This organization is for individuals who appreciate challenging themselves and thrive on curiosity. We operate with a flat organizational structure. All employees are expected to be hands-on and to contribute directly to the company's mission. Leadership is given to those who show initiative and consistently deliver excellence. Work ethic and strong prioritization skills are important. All employees are expected to have strong communication skills. They should be able to concisely and accurately share knowledge with their teammates. ABOUT THE ROLE: We are building one of the world's largest AI supercomputers from the ground up. As part of the Compute Infrastructure team, you will own both the raw GPU supercomputer and the platform layer that runs on top of it. You will work across the full stack - from low-level GPU kernel optimizations and Linux kernel internals to massive-scale orchestration and virtualization - to make training and inference at xAI as fast, reliable, and scalable as possible. This is a broad, high-impact role that combines hardcore supercompute and compute infrastructure work. Your contributions will directly accelerate Grok's training speed and overall AI progress. RESPONSIBILITIES : - Design, build, and optimize massive GPU clusters for extreme-scale training and inference workloads - Develop and tune low-level CUDA
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Collateral Design and DFM Engineer
Intel - 3 LocationsIndexed from Workday Benefit evidence checked Jun 13, 2026posted 120 days agoWhy we showed this
Employer: "intel"Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedCollateral Design and DFM Engineer 3 Locations posted: Posted 8 Days Ago
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Staff FPGA Engineer, Intelligence Systems
Anduril - Reston, Virginia, United StatesIndexed from Greenhouse Comp disclosed in postingposted 177 days agoWhy we showed this
Title: "intel"Role: semantic matchUnspecified Engineering From the posting source - Staff Plus From the posting source $220K-$292K From the posting source Equity Secret clearanceStaff FPGA Engineer, Intelligence Systems Reston, Virginia, United States Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years. WHAT IS AIS? Anduril Intelligence Systems (AIS) is focused on positioning Anduril as a lead provider of specialized engineering and products for Intelligence Community (IC) customers. We work within the IC to understand their requirements, shape their concepts of operation, and deliver exquisite capability across their problem set. We aim to develop and deploy critically needed capabilities that address our customers' most pressing national security requirements. ABOUT THE JOB We are looking for a Staff FPGA Engineer to join our rapidly growing team in Reston, Virginia . You will be responsible for rapidly developing, testing, and implementing FPGA designs on Xilinx SoC/FPGA platforms. This requires strong skills in digital circuit design, VHDL/Verilog coding, and simulation. WHAT YOU'LL DO - Integrate third-party vendors IP, as necessary. - Participate in entire design life cycle: from
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Manufacturing Bring-up Engineer L2
Cerebras Systems - Bengaluru, Karnataka, India; Sunnyvale, CA; Toronto, Ontario, CanadaIndexed from Greenhouse Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 213 days agoWhy we showed this
Description: "intel"Role: semantic matchUnspecified Operations From the posting source - Mid From the posting source $170K-$230K From the posting source Equity Inferred from posting 401(k) reportedManufacturing Bring-up Engineer L2 Bengaluru, Karnataka, India; Sunnyvale, CA; Toronto, Ontario, Canada Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. The Role We are seeking a highly skilled and motivated Manufacturing Bring-up Engineer to join our team. As the Manufacturing Bring-up Engineer you will support our system level bring-up process execution, implementation, and evolution in the manufacturing pipeline. This is a high visibility role that requires strong technical expertise, coordination, and collaboration to deliver our product from manufacturing to the customer. Responsibilities - Support the Cerebras manufacturing bring-up process execution to configure, test, and validate system performance prior to customer
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CPU Logic Equivalence Check (LEC) Engineer
Apple - Santa Clara, United States of AmericaIndexed from Apple Custom Benefit evidence checked Jun 13, 2026 Comp disclosed in postingposted 170 days agoWhy we showed this
Role: semantic matchUnspecified Engineering From the posting source - Mid From the posting source $181K-$318K From the posting source Equity Inferred from posting 401(k) reportedCPU Logic Equivalence Check (LEC) Engineer Santa Clara, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple's Silicon Engineering Group (SEG) is looking for a hardworking engineer for CPU gate level verification team. In this role, the candidate would be part of Apple's industry-leading CPU design team, working in a multi-functional role to design verification flows and ensure that our CPUs meet the highest standards for functional verification. You will own the logic equivalence check and sign-off of Apple's high-performance CPU projects. Responsibilities include but are not limited to: • Developing and improving existing flow for logical equivalent check • Running and signing off block and top level logic equivalence checks, structural gate checks, and low power checks • Supporting the design team in block level verification runs and debug • Working closely with design/CAD teams on the methodology for verification of new features • Creating scripts to automate verification runs and track the results of
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Design Automation Engineer (TFM/EDA)
Intel - 4 LocationsIndexed from Workday Benefit evidence checked Jun 13, 2026posted 120 days agoWhy we showed this
Employer: "intel"Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedDesign Automation Engineer (TFM/EDA) 4 Locations posted: Posted 8 Days Ago
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CPU Implementation Engineer
Apple - Beaverton, United States of AmericaIndexed from Apple Custom Benefit evidence checked Jun 13, 2026 Comp disclosed in postingposted 172 days agoWhy we showed this
Role: semantic matchUnspecified Engineering From the posting source - Mid From the posting source $181K-$318K From the posting source Equity Inferred from posting 401(k) reportedCPU Implementation Engineer Beaverton, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation. As a CPU Implementation Engineer, you will drive or participate in the following: • Work with micro-architects to help define the micro-architecture and assist with design feasibility and power, performance, and area (PPA) trade-offs • Drive RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations using synthesis and place-and-route tools targeting ambitious goals for PPA • Responsible for block-level design delivery along with closure of backend flows, electrical requirements, and improving silicon yield • Work closely with internal CAD and PD methodology teams on industry-standard synthesis/PNR tool features and optimizations and their adoption in CPU design • Work with x-functional top-level teams on the aspects of CPU floorplan, timing, power, reliability, and testability • Work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve
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DevOps & Cloud Infrastructure Engineer
Intel - Israel, HaifaIndexed from Workday Benefit evidence checked Jun 13, 2026posted 120 days agoWhy we showed this
Employer: "intel"Unspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedDevOps & Cloud Infrastructure Engineer Israel, Haifa posted: Posted 8 Days Ago
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Hardware Design – AI Ecosystem Enabling Intern
Intel - Mexico, GuadalajaraIndexed from Workday Benefit evidence checked Jun 13, 2026posted 143 days agoWhy we showed this
Employer: "intel"Role: semantic matchUnspecified Design From the posting source - Entry From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedHardware Design – AI Ecosystem Enabling Intern Mexico, Guadalajara posted: Posted 30+ Days Ago
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Lead Senior Design Engineer – AI SoC Development
Intel - 3 LocationsIndexed from Workday Benefit evidence checked Jun 13, 2026posted 143 days agoWhy we showed this
Employer: "intel"Role: semantic matchUnspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedLead Senior Design Engineer – AI SoC Development 3 Locations posted: Posted 30+ Days Ago
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PDK Development Technical Manager
Intel - Malaysia, PenangIndexed from Workday Benefit evidence checked Jun 13, 2026posted 143 days agoWhy we showed this
Employer: "intel"Unspecified Engineering From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedPDK Development Technical Manager Malaysia, Penang posted: Posted 30+ Days Ago
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Network Security Engineer
Intel - US, Arizona, PhoenixIndexed from Workday Benefit evidence checked Jun 13, 2026posted 135 days agoWhy we showed this
Employer: "intel"Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedNetwork Security Engineer US, Arizona, Phoenix posted: Posted 23 Days Ago
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Applied AI/ML Scientist
Cerebras Systems - UAEIndexed from Greenhouse Benefit evidence checked Jun 7, 2026posted 260 days agoWhy we showed this
Description: "intel"Role: semantic matchUnspecified Data From the posting source - Mid From the posting source Salary not disclosed Inferred from posting 401(k) reportedApplied AI/ML Scientist UAE Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. About The Role As an Applied AI Scientist in the FieldML team, you will be responsible for developing and customizing large language models and more broadly large-scale deep learning models to solve specific customer problems. You won't just advise; you will build. You will bridge the gap between state-of-the-art research and real-world applications by helping customers harness the power of the Cerebras Wafer-Scale Engine (WSE) for their AI initiatives. We are looking for experienced AI Scientists who are passionate about the "applied" side of machine learning - those
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Network Engineer
Cerebras Systems - Sunnyvale, CA; Toronto, Ontario, CanadaIndexed from Greenhouse Benefit evidence checked Jun 7, 2026posted 120 days agoWhy we showed this
Description: "intel"Role: semantic matchUnspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Inferred from posting 401(k) reportedNetwork Engineer Sunnyvale, CA; Toronto, Ontario, Canada Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. About The Role We are looking for a Network Architect to join our Cluster Engineering Team and help shape the front-end datacenter and interconnect fabric for the current and next generations of our AI clusters. You will partner closely with hardware vendors, internal networking teams, and industry peers to define best-in-class network architectures that deliver resilient, reliable, and high-throughput connectivity for large-scale AI workloads. This is a deeply technical role that spans the full stack, from host-side networking and NIC behavior up through cluster-level coordination
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Graduate Talent (Memory Design)
Intel - Malaysia, PenangIndexed from Workday Benefit evidence checked Jun 13, 2026posted 143 days agoWhy we showed this
Employer: "intel"Unspecified Hr From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedGraduate Talent (Memory Design) Malaysia, Penang posted: Posted 30+ Days Ago
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Device Driver validation Engineer
Intel - India, BangaloreIndexed from Workday Benefit evidence checked Jun 13, 2026posted 123 days agoWhy we showed this
Employer: "intel"Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedDevice Driver validation Engineer India, Bangalore posted: Posted 11 Days Ago
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Analytical Chemistry Lab Technician
Intel - US, Oregon, HillsboroIndexed from Workday Benefit evidence checked Jun 13, 2026posted 112 days agoWhy we showed this
Employer: "intel"Unspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedAnalytical Chemistry Lab Technician US, Oregon, Hillsboro posted: Posted Today
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Senior CPU Core Physical Design Engineer
Intel - US, California, FolsomIndexed from Workday Benefit evidence checked Jun 13, 2026posted 143 days agoWhy we showed this
Employer: "intel"Role: semantic matchUnspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedSenior CPU Core Physical Design Engineer US, California, Folsom posted: Posted 30+ Days Ago
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Staff Software Engineer, Inference Cloud
Cerebras Systems - Sunnyvale, CAIndexed from Greenhouse Benefit evidence checked Jun 7, 2026posted 812 days agoWhy we showed this
Description: "intel"Role: semantic matchUnspecified Engineering From the posting source - Staff Plus From the posting source Salary not disclosed Inferred from posting 401(k) reportedStaff Software Engineer, Inference Cloud Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Location: Sunnyvale We're hiring a Staff Engineer to own major areas of the architecture of our Inference Cloud Platform. This team owns the cloud layer behind our Inference Service, with responsibility for availability, latency, reliability, and global scale. This is a hands on IC role for an engineer who wants to work on the hardest distributed systems problems in the stack: multi-region traffic architecture, graceful degradation under bursty AI workloads, performance at high QPS, and the operating model for a platform that has to stay
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