CPU Logic Equivalence Check (LEC) Engineer
Apple - Santa Clara, United States of America
Posted Apr 14, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
- Not verified
- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
- Not verified
- Relocation assistance
- Not verified
- Childcare support
- Not verified
- Learning budget
- Not verified
- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified not verified - source not recorded; timestamp not recorded
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
CPU Logic Equivalence Check (LEC) Engineer Santa Clara, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple's Silicon Engineering Group (SEG) is looking for a hardworking engineer for CPU gate level verification team. In this role, the candidate would be part of Apple's industry-leading CPU design team, working in a multi-functional role to design verification flows and ensure that our CPUs meet the highest standards for functional verification. You will own the logic equivalence check and sign-off of Apple's high-performance CPU projects. Responsibilities include but are not limited to: • Developing and improving existing flow for logical equivalent check • Running and signing off block and top level logic equivalence checks, structural gate checks, and low power checks • Supporting the design team in block level verification runs and debug • Working closely with design/CAD teams on the methodology for verification of new features • Creating scripts to automate verification runs and track the results of
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