NXP Semiconductors jobs
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Photolithography Equipment Engineer - TEL Tracks/Spinners
NXP Semiconductors - Austin (Ed Bluestein, Office)Indexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPhotolithography Equipment Engineer - TEL Tracks/Spinners Austin (Ed Bluestein, Office) posted: Posted 30+ Days Ago
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Principal IP Licensing Manager (Technical Program Management)
NXP Semiconductors - Austin (Oakhill, Office)Indexed from Workday Benefit evidence checked May 7, 2026posted 85 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"+1
Unspecified Engineering From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal IP Licensing Manager (Technical Program Management) Austin (Oakhill, Office) posted: Posted 17 Days Ago
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Senior Shift Technician
NXP Semiconductors - Kuala LumpurIndexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Shift Technician Kuala Lumpur posted: Posted 30+ Days Ago
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Principal AMS Verification Engineer
NXP Semiconductors - BangaloreIndexed from Workday Benefit evidence checked May 7, 2026posted 96 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal AMS Verification Engineer Bangalore posted: Posted 28 Days Ago
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Senior Principal Data and AI Engineer- R&D IT
NXP Semiconductors - BangaloreIndexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Principal Data and AI Engineer- R&D IT Bangalore posted: Posted 30+ Days Ago
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Senior Principal SoC Physical Implementation/STA Engineer
NXP Semiconductors - 2 LocationsIndexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Principal SoC Physical Implementation/STA Engineer 2 Locations posted: Posted 30+ Days Ago
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Lead Hardware Engineer
Eaton Corporation - Xian, Shaanxi, CHN, 710077Indexed from Eightfold Benefit evidence checked Jun 13, 2026posted 68 days agoWhy we showed this
Role: semantic matchUnspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedLead Hardware Engineer Xian, Shaanxi, CHN, 710077
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2026 Intern - Accounting
NXP Semiconductors - Kuala LumpurIndexed from Workday Benefit evidence checked May 7, 2026posted 76 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"Unspecified Finance From the posting source - Entry From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reported2026 Intern - Accounting Kuala Lumpur posted: Posted 8 Days Ago
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ASIC Design Engineer (eInfochips)
Arrow Electronics - Mountain View, California, United States of AmericaIndexed from Phenom People Benefit evidence checked Jun 7, 2026posted 84 days agoWhy we showed this
Role: semantic matchUnspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedASIC Design Engineer (eInfochips) Mountain View, California, United States of America Embrace the role of an ASIC Design Engineer and drive innovation in high-speed FPGA design. Leverage your expertise in Verilog, ASIC tools, and industry protocols to deliver cutting-edge solutions. Collaborate with top engineers, work on ARM and AXI designs, and make a real impact in advanced semiconductor technology. Grow your career with us!
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Data Platform DevOps Engineer
NXP Semiconductors - BangaloreIndexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedData Platform DevOps Engineer Bangalore posted: Posted 30+ Days Ago
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Photonics Fabrication Process Engineer - SNSPD Nanofabrication
Xanadu - Location not specifiedIndexed from Jazzhrposted 70 days agoWhy we showed this
Role: semantic matchPhotonics Fabrication Process Engineer - SNSPD Nanofabrication Photonics Fabrication Process Engineer - SNSPD Nanofabrication
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NMSi- F11x Dry Etch Module Group Leader
Intel - US, New Mexico, AlbuquerqueIndexed from Workday Benefit evidence checked Jun 13, 2026posted 71 days agoWhy we showed this
Role: semantic matchUnspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedNMSi- F11x Dry Etch Module Group Leader US, New Mexico, Albuquerque posted: Posted 3 Days Ago
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Business Development Manager (f/m/d)
NXP Semiconductors - MunichIndexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"Unspecified Sales From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedBusiness Development Manager (f/m/d) Munich posted: Posted 30+ Days Ago
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Interconnect NPI Product Engineer
NVIDIA Corporation - Israel, YokneamIndexed from Workday Benefit evidence checked Jun 13, 2026posted 70 days agoWhy we showed this
Role: semantic matchUnspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedInterconnect NPI Product Engineer Israel, Yokneam posted: Posted 2 Days Ago
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Principal Analog IP Design Lead - MCU
NXP Semiconductors - CataniaIndexed from Workday Benefit evidence checked May 7, 2026posted 77 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"+1
Unspecified Design From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Analog IP Design Lead - MCU Catania posted: Posted 9 Days Ago
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Director – Export Control and Sanctions Compliance
NXP Semiconductors - Austin (Oakhill, Office)Indexed from Workday Benefit evidence checked May 7, 2026posted 97 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"+1
Unspecified Finance From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedDirector – Export Control and Sanctions Compliance Austin (Oakhill, Office) posted: Posted 29 Days Ago
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2026 Intern- Digital/Mixed-signal Design Intern
NXP Semiconductors - Tianjin (Teda)Indexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"+1
Unspecified Marketing From the posting source - Entry From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reported2026 Intern- Digital/Mixed-signal Design Intern Tianjin (Teda) posted: Posted 30+ Days Ago
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Chandler Fab Office Manager
NXP Semiconductors - Chandler (Office)Indexed from Workday Benefit evidence checked May 7, 2026posted 89 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"Unspecified Other - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedChandler Fab Office Manager Chandler (Office) posted: Posted 21 Days Ago
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Principal Engineer, ASIC Development Engineering (Mixed-Signal IP Layout)
SanDisk - Bengaluru, KA, IndiaIndexed from Smartrecruitersposted 70 days agoWhy we showed this
Role: semantic matchUnspecified Engineering From the posting source - Principal From the posting source Salary not disclosed EquityPrincipal Engineer, ASIC Development Engineering (Mixed-Signal IP Layout) Bengaluru, KA, India Company Description: Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description: We are looking for technically sound and highly skilled Analog/High Speed DDR IO Layout designer with 8-12 years of experience. The ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize MSIP IC layouts in TSMC 3nm, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements
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Films Equipment Engineer - Novellus C2
NXP Semiconductors - Austin (Ed Bluestein, Office)Indexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedFilms Equipment Engineer - Novellus C2 Austin (Ed Bluestein, Office) posted: Posted 30+ Days Ago
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Senior Accountant & SOX Specialist
NXP Semiconductors - Kuala LumpurIndexed from Workday Benefit evidence checked May 7, 2026posted 99 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"Unspecified Finance From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Accountant & SOX Specialist Kuala Lumpur posted: Posted 30+ Days Ago
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ASIC Engineering Analog Design Leader | high-speed optical transceiver circuits (modulator drivers, TIAs, CDRs, PLLs, ADC/DAC) | 12+ years, Bangalore
Cisco - Bangalore, IndiaIndexed from Workday Benefit evidence checked Jun 13, 2026posted 68 days agoWhy we showed this
Role: semantic matchApply link reachable when checkedUnspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedASIC Engineering Analog Design Leader | high-speed optical transceiver circuits (modulator drivers, TIAs, CDRs, PLLs, ADC/DAC) | 12+ years, Bangalore Bangalore, India Cisco's Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG's ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry. You will work with Cisco's best-in-class Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures. We seek an experienced High Speed AMS Design Engineer to lead full-chip electrical specifications and mixed-signal design for Cisco's silicon photonics driver integrated circuits supporting 100G/200G/400G per Lambda solutions. You will own high-speed datapath and low-speed control circuit design for receive and transmit paths in our next-generation silicon photonics modules. Your Impact As a High-Speed Analog/Mixed-Signal (AMS) Design Leader, you will play a pivotal role in shaping next-generation silicon photonics driver ICs. You will: Lead full-chip electrical architecture, specifications, and execution for high-speed silicon photonics driver
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Device Engineer (Einfochips Inc)
Arrow Electronics - Peachtree City, Georgia, United States of AmericaIndexed from Phenom People Benefit evidence checked Jun 7, 2026posted 113 days agoWhy we showed this
Role: semantic matchUnspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedDevice Engineer (Einfochips Inc) Peachtree City, Georgia, United States of America Embrace the role of a Device Engineer and drive innovation in automotive software solutions. Collaborate with cross-functional teams, design secure Android and Linux platforms, and ensure seamless integration of vehicle systems. Shape the future of automotive technology with eInfochips and make a real impact on next-generation mobility solutions.
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Electrical Engineer FPGA/ASIC - Level 3/4 - Dulles
Northrop Grumman Corporation - United States-Virginia-DullesIndexed from Eightfold Benefit evidence checked Jun 7, 2026posted 68 days agoWhy we showed this
Role: semantic matchUnspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedElectrical Engineer FPGA/ASIC - Level 3/4 - Dulles United States-Virginia-Dulles
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