ASIC Design Verification Technical Leader

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified

Salary

Not verified

401(k) match

Not verified

Was this benefit information wrong? Tell us.

Market context

U.S. role benchmark (BLS OEWS)

$66,396 U.S. median for this role

Projected growth (BLS Employment Projections)

+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Design From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Design Verification Technical Leader Carlsbad, California, United States of America Embrace the role of a Design Verification Technical Leader and drive the verification of next-generation silicon photonics modules. Leverage your expertise in UVM, RTL design, and Python to develop testbench components, functional tests, and coverage models. Collaborate with cross-functional teams and play a key role in advancing cutting-edge digital solutions.

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.