ASIC Design Verification Emulation Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

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Salary

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401(k) match

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Market context

U.S. role benchmark (BLS OEWS)

$66,396 U.S. median for this role

Projected growth (BLS Employment Projections)

+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Design From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

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Weekend work

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Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Design Verification Emulation Engineer San Jose, California, United States of America Exciting opportunity for an ASIC Design Verification Emulation Engineer and drive innovation in ASIC verification for cutting-edge AI and networking solutions. Lead technical teams, shape verification strategies, and influence industry best practices. If you have deep expertise in ASIC emulation, system verilog, and leadership, this is your opportunity to make a global impact.

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.