Semiconductor Design Engineer (Teradyne, Costa Rica)

Benefits

Parental leave

4 weeks From the posting source checked Jun 20, 2026

Non-birth-parent leave

4 weeks From the posting source checked Jun 20, 2026

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Offered From the posting source checked Jun 20, 2026

Learning budget

Not verified

Verification

Source-linked checked May 7, 2026

Salary

Not verified

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Senior From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Semiconductor Design Engineer (Teradyne, Costa Rica) Semiconductor Design Engineer (Teradyne, Costa Rica) We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Opportunity Overview We're looking for a highly experienced Senior Analog Layout Engineer to join our semiconductor design team. In this role, you will lead the physical layout and verification of complex analog and mixed-signal ASICs in advanced FinFET technologies, helping deliver the next generation of Teradyne's test and automation platforms. You'll collaborate closely with circuit designers, physical design engineers, and cross-functional partners to create high-quality, manufacturable layouts that meet demanding performance, reliability, and schedule targets. Key Responsibilities Lead the layout design and integration of complex analog and mixed-signal ASIC blocks using Cadence Virtuoso. Develop floorplans, placement, routing, and top-le

Read the full description at jobs.teradyne.com. FewerJobs shows a preview and links to the original posting.