Analog Design Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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Mental health support

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

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Weekend work

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Application

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Assessment

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Deadline

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About this role

Analog Design Engineer North America Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an experienced Analog Design Engineer to develop cutting-edge die-to-die chiplet PHY IP solutions that power the future of AI computing. You'll work at the forefront of deep sub-micron technologies, collaborating with circuit architects and cross-functional teams to push the boundaries of analog/mixed-signal design. If you have a proven track record of delivering production-quality silicon and want to innovate at the heart of next-generation interconnects, join our team. This role is remote, based out of any in North America . We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are - A Analog/Mixed-Signal Design Engineer to develop die-to-die chiplet PHY IP, including PLLs and key analog/mixed-signal blocks in deep sub-micron FinFET technologies. - A hands-on owner for the full lifecycle: design, verification, layout

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