Digital Verification Development Engineer

Benefits

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Mid From the posting source

Schedule

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Weekend work

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Deadline

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About this role

Digital Verification Development Engineer Cairo, Cairo Governorate, Egypt Company Description: Mixel, a Silvaco Company, is an innovator of high-performance analog mixed signal semiconductor IPs whose solutions are powering Mobile, Display, Camera, Automotive, VR, AR and AI applications. Our mission is to provide our customers and partners with outstanding mixed-signal, silicon-proven IPs, creating in the process a differentiating technology that sets your products apart. At Mixel, you will find an inspiring environment with a strong focus on technical innovation, people well-being, no layers of management, and the freedom to make meaningful contributions in a setting that encourages creative thinking. We value open communication, empathy, mutual trust, and respect. Job Description: Develop test plan from specification and architect system level verification environments. Develop and maintain UVM-based testbenches for block-level and subsystem-level verification Write constrained-random stimulus, scoreboards, monitors, and coverage models in SystemVerilog Contribute to regression infrastructure, continuous integration flows, and internal verification methodology Drive functional and code coverage closure; analyze coverage holes and add targeted tests Integrate and configure VIP (Verification IP) for standard protocols Support FPGA-based prototyping and pre-silicon bring-up with validation test suites Execute RTL/Gate level simulations and analyze results. Contribute to design/verification process automation. Qualifications: Essential Qualifications and Experience: Bachelor's degree of: Electronics/Computer Engineering. Years of experience in the same field: 0-3 Years of experience in developing SV-based verification environments. Strong knowledge of Verilog, System Verilog, and object-oriented programming languages. Strong proficiency in UVM methodology Solid understanding of functional and code coverage metrics and closure English Language Proficiency: Fluency

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