Digital Design Engineer

Benefits

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Mid From the posting source

Schedule

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Weekend work

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Application

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Deadline

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About this role

Digital Design Engineer Cairo, Cairo Governorate, Egypt Company Description: Mixel, a Silvaco Company, is an innovator of high-performance analog mixed signal semiconductor IPs whose solutions are powering Mobile, Display, Camera, Automotive, VR, AR and AI applications. Our mission is to provide our customers and partners with outstanding mixed-signal, silicon-proven IPs, creating in the process a differentiating technology that sets your products apart. At Mixel, you will find an inspiring environment with a strong focus on technical innovation, people well-being, no layers of management, and the freedom to make meaningful contributions in a setting that encourages creative thinking. We value open communication, empathy, mutual trust, and respect. Job Description: Develop a thorough understanding of system-level design specifications Verilog RTL Coding, Synthesis, Simulation of the digital IPs Develop advanced verification environment and test-bench components Conduct RTL linting, CDC/RDC checks, and formal verification as part of the sign-off flow Perform synthesis, timing analysis, and work with physical design teams on DFT and timing closure Hardware verification of the digital module using cutting edge FPGA kits Gate level verification of digital IPs Qualifications: Essential Qualifications and Experience: Bachelor's degree of: Electronics Engineering, M.Sc. in Electronics Engineering is a plus 0-3 Years of experience in VLSI Digital Design/Verification, gate verification techniques is a plus Strong knowledge of Verilog RTL design/simulation Knowledge of clock domain crossing (CDC) and reset domain crossing (RDC) techniques Knowledge of ASIC/FPGA design flows including RTL Synthesis, Place and Route, and Timing Sign-off Solid understanding of static timing analysis (STA) and timing

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