Experienced PCIe System Design Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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Mental health support

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Mid From the posting source

Schedule

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Weekend work

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Company

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Application

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Deadline

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About this role

Experienced PCIe System Design Engineer Kfar Saba, Center District, Israel Company Description: Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description: We are looking for a hands-on System Engineer, focused on the design, implementation, and silicon validation of PCIe interfaces within our SoC. The role requires a deep understanding of protocol layers, detailed design of the controller and its integration, and performing deep-level hardware debugging and silicon bring-up to ensure high-speed connectivity and NVMe compatibility. Key Responsibilities PCIe Design & Configuration: Defining and implementing PCIe Controller and PHY IP Protocol Logic

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