Staff Digital Design Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 7, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Mid From the posting source

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

Staff Digital Design Engineer Edinburgh, , United Kingdom Company Description: Job Description: We are actively seeking a highly skilled and motivated Staff Digital Design Engineer to join our growing hardware development team. In this role, you will be responsible for designing power and area optimised digital circuits for complex mixed-signal applications. You will work closely with analog and verification engineers to deliver high-quality silicon solutions. Job Purpose & Dimensions: Interpret high level requirements to architect, design & integrate low-power digital circuits for mixed-signal data conversion and power management products in advanced process nodes Support full product lifecycle from concept to mass-production; communicating closely with wider organisation through the various stages of silicon development Provide technical leadership & influence to the digital design team by contributing to technical discussions & reviews, mentoring junior engineers, and supporting recruitment Responsibilities Ensuring digital development process is state-of-art and achieves budget, schedule, and project deliverable goals Designing digital RTL that meets timing, area, power and any adhering standards specifications Integrating design at the top level and running block & top-level simulations Participate in all aspects of Mixed-signal design flow - Micro-architecture, Design partitioning, RTL Verilog / SystemVerilog Design, Generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC, RDC, UPF Working closely with P&R team to generate a layout that meets timing, area, and power requirements Support DFT strategy and implementation, and review test case development Assisting with top level test-bench debug, and running RTL & gate level simulations Working with analog and

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