Staff Analog Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 7, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Mid From the posting source

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Staff Analog Engineer Edinburgh, , United Kingdom Company Description: Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world's leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Job Description: Design and verify CMOS major analog blocks for custom ASICs to meet performance, area, power and timescale constraints. Take technical leadership of full-chip or major system level blocks and drive projects from specification to production ramp. Collaborate with analogue and digital leads to achieve system and design strategy for custom ASICs and drive layout team to high quality physical implementation. Produce high quality documentation for designed circuits. Work closely with DFT engineers to ensure alignment to DFT strategy and implementation. Drive silicon debugging and design characterisation. Work with test and product engineers to support test development and ramp to production. Take a proactive approach to driving own development plan, utilising team members and internal development opportunities. Maintain technical project involvement at principal level and drive consistent methodology engagement across the team. Design and verify analog block-level, sub-system and chip-level circuits to meet the functional and

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