Sr Principal Engineer, PD Expert (MCU and derivative devices)

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 7, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

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Seniority

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Schedule

Shift type

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Weekend work

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Application

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

Sr Principal Engineer, PD Expert (MCU and derivative devices) Austin, TEXAS, United States Company Description: This role is a senior technical authority responsible for defining, aligning, and governing Physical Design Architecture, Technology aspects, Foundry selection & PPA. The technologist serves as the primary interface between the internal SoC Physical Design organization and the foundry, systems team & ensure competitive edge. Job Description: Foundry (TSMC) Interface & Ownership Primary technical point of contact with TSMC for Physical Design. Technical discussions with foundry team internal and external with regards to foundry selection Work with foundry & technology to define requirements for signoff & collaterals. AI Initiative Lead an AI initiative focusing cost reduction of MCU development Drive the AI strategy of Physical team in conjunction with methodology teams and external vendors. Pilot AI initiatives within organization including scoping, definition & implementation. Physical Design Architecture Definition and Feasibility Work with system architects, Architecture team & Chip leads to ensure physically realizable architecture for MCU designs Drive Physical Partitioning, latency, pipeline planning, IO & AC requirement with leads. Align Die-size & PPA targets & KPI for SoC/MCUs Qualifications: Master's degree in electrical, Electronics, or Computer Engineering. 18-20+ years of experience in Physical Design with multiple -node tapeouts. Experience handling MCU designs, Familiarity with Architecture & Design Additional Information: Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to

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