Sr Mask Design Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 7, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Senior From the posting source

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

Sr Mask Design Engineer Bengaluru, KA, India Company Description: Renesas Electronics India (REIN) is a dynamic, multi-cultural tech company where employees can learn, mentor and thrive. REIN brings together the strong financial foundation of a multi-billion dollar global operation and the flexibility and velocity of a smaller organization. We are developing technologies for the latest advances in electric vehicles, autonomous driving, mobile computing, secured connected devices, smart homes and factories and more. Our solutions are at the heart of products developed by the major innovators around the world. Join us and be part of what's next in electronics. Job Description: Job Responsibilities: Layout high performance Analog and Mixed Signal circuits using the latest Cadence Design Suite Perform IP level layout tasks including device placement, routing, matching techniques, shielding, guard rings, and parasitic-aware layout practices. Work at multiple levels of hierarchy, from macro level (block level) to Top-level (ESD/Pad frame) Verify connectivity and design rules with Assura, Calibre, PVS Use QRC extraction to analyze and reduce noisy/sensitive coupling Use third party tools to analyze IR drops and p2p resistance Liaise closely with analog designers on specific circuit requirements, e.g. power, matching, sensitivity, latch-up, ESD, etc. Work with CAD and CAE engineers to improve processes or features Qualifications: Job Requirements: BE/BTech in Electrical or Electronic Engineering is preferred. A minimum of two to five years industry experience working on analog, power or mixed signal IC layouts A good working knowledge of Analog IC layout and verification tools Experience in “routing” using latest

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