Senior Staff Digital Design Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 7, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Senior From the posting source

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

Senior Staff Digital Design Engineer Prague, , Czechia Company Description: Job Description: We are seeking a highly experienced Digital Design Engineer to join our IC development team and contribute to our successful record of defining and developing market leading complex power management solutions. Job duties: Collaborate with marketing and customers to define system-level requirements and IC specifications Propose innovative and creative solutions to achieve the required specifications Develop, debug and verify digital designs in pre and post silicon environment Oversee digital backend design, including synthesis, STA, P&R and logic equivalence checking Collaborate on block integration in complex mixed-signal designs Coach and mentor junior team members Qualifications: 12+ years of relevant industry experience in FPGA or IC design MSc/PhD university degree Proficiency in HDL languages - Verilog, SystemVerilog or VHDL Experience in architecting digital designs and writing device-level or sub-system specifications Competence in developing design constraints for synthesis, STA and P&R hand-off Experience with gate-level simulations and debug Knowledge of advanced verification methodologies (e.g. UVM) Good communication skills in English Will be a plus : Proficient in programming/scripting (Perl, Python, Skill, TCL, C/C++, etc.) Exposure to mixed signal designs with basic understanding of analog circuits Expertise in digital backend design flow (synthesis / STA / P&R) Familiarity with DFT insertion and ATPG generation Working experience with Cadence or Synopsys design tools Experience implementing and verifying ECOs on post-route netlist Additional Information: Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the

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