Principal Engineer, Router Architect
Renesas Electronics - Austin, TEXAS, United States
Posted Jun 10, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
- Not verified
- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
- Not verified
- Relocation assistance
- Not verified
- Childcare support
- Not verified
- Learning budget
- Not verified
- Verification
- Not verified checked Jun 7, 2026
- Salary
- Not verified
- 401(k) match
- Reported from DOL Form 5500 industry filing (not employer-specific)
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Market context
- U.S. role benchmark (BLS OEWS)
- $111,944 U.S. median for this role
- Projected growth (BLS Employment Projections)
- +13.7% - Much faster than average
Matched to SOC 15-1252 - Data and ML aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Schedule
- Shift type
- Not verified
- Weekend work
- Not verified
Application
- Cover letter
- Not verified
- Assessment
- Not verified
- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Principal Engineer, Router Architect Austin, TEXAS, United States Company Description: Job Description: We are seeking a Principal Router Architect with 10 to 15 years of experience to define the backbone of next-generation Zonal and Central Compute Automotive architectures . This role focuses on architecting high-bandwidth, ultra-reliable Ethernet Routing Engines and PCIe subsystems that serve as the primary data fabric for Autonomous Driving (AD) and Cockpit controllers. The ideal candidate will bridge the gap between high-speed data center-grade throughput and the rigorous Safety (ISO 26262) and Deterministic Networking requirements of the automotive industry. Responsibilities: Automotive Ethernet Routing : Architect L2/L3 switch fabrics supporting Time-Sensitive Networking (TSN) standards (e.g., IEEE 802.1AS, 802.1Qbv, 802.1Qbu) to ensure deterministic latency for safety-critical traffic. PCIe Backbone Architecture : Define PCIe Gen 5/6 integration for high-speed chip-to-chip connectivity between SoCs, AI accelerators, and storage, including support for SR-IOV to virtualize resources across multiple Virtual Machines (VMs). Functional Safety (ASIL) : Integrate hardware safety mechanisms (ECC, Parity, BIST, and End-to-End protection) to meet ASIL-B/D requirements within the routing engine and bus fabrics. Zonal Interconnect & Bus Fabric : Design the interface between Ethernet/PCIe controllers and internal NoC/CHI fabrics , ensuring efficient data movement for ADAS sensors (Camera, LiDAR) and telemetry. Virtualization & Security : Architect hardware-assisted isolation and Secure On-board Communication (SecOC) to protect the vehicle network from cyber threats while allowing shared access to network resources. Infrastructure & Power : Define robust clock, reset, and power management schemes capable of operating under automotive thermal profiles and supporting
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