Principal Engineer, Compiler
Renesas Electronics - Kodaira, , Japan
Posted Jun 12, 2026
Benefits
- Parental leave
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- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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Market context
- U.S. role benchmark (BLS OEWS)
- $111,944 U.S. median for this role
- Projected growth (BLS Employment Projections)
- +13.7% - Much faster than average
Matched to SOC 15-1252 - Data and ML aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Schedule
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- Weekend work
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Application
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- Deadline
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About this role
Principal Engineer, Compiler Kodaira, , Japan Company Description: Job Description: As an AI Compiler Engineer on the Renesas HPC team, you will be responsible for driving compiler and code generation technologies that unlock the full compute potential of Renesas next-generation automotive System-on-Chip platforms, including advanced 3 nm silicon for software-defined vehicles (SDVs). Your work will directly impact how AI workloads - from perception and sensor fusion to in-vehicle assistants and advanced driver assistance - are translated into highly optimized, safe, and power-efficient execution on Renesas hardware. This role bridges software compiler development, AI model lowering/optimization, and hardware-software co-design, enabling Renesas SoCs to deliver industry-competitive performance, efficiency, and functional safety required by multi-domain automotive applications.. 【Job Description】 ・Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration ・Design and implement graph‑level optimizations (operator fusion, quantization‑aware rewrites, memory‑aware scheduling, partitioning) ・Drive performance optimization for target NPUs, including tiling, tensor layout, and multi‑core execution strategies ・Partner with SoC and AI accelerator architects to influence hardware features through compiler insights ・Own performance KPIs for real automotive AI workloads using simulators, profilers, and silicon‑correlated models ・Ensure compiler outputs meet automotive requirements (real‑time behavior, determinism, quality expectations) ・Mentor senior engineers and set technical direction without people‑management responsibilities 【Impact & Differentiators】 Renesas' Gen5 R-Car automotive SoC lineup, including flagship 3 nm devices like the R-Car X5H, is among the first highly integrated multi-domain automotive SoCs built on advanced 3 nm process technology, designed to run ADAS, IVI, gateway, and next-gen SDV workloads
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