Senior ASIC Design Engineer, Memory Controller

Verified benefits

Parental leave

12 weeks source

Non-birth-parent leave

12 weeks

Verified

Yes last checked unknown

Salary

Not disclosed

Market context

Median wage (BLS OEWS)

$81,680 national median

Projected growth (BLS Employment Projections)

+4.6% - Average

Matched to SOC 13-2011 - Accountants and Auditors by title.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Senior ASIC Design Engineer, Memory Controller US, CA, Santa Clara Senior ASIC Design Engineer, Memory Controller /job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer--Memory-Controller_JR2010019-1 US, CA, Santa Clara Posted 7 Days Ago

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