Senior FPGA / RTL Design Engineer - Signal Processing

Verified benefits

Parental leave

13 weeks source

Non-birth-parent leave

13 weeks

Verified

Yes last checked 2026-05-07

Salary

Not disclosed

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Senior FPGA / RTL Design Engineer - Signal Processing Los Angeles, CA, More... Senior FPGA / RTL Design Engineer - Signal Processing /job/Los-Angeles-CA/Senior-FPGA---RTL-Design-Engineer---Signal-Processing_R63336 Los Angeles, CA, More... Posted 27 Days

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