Senior Semiconductor Design Engineer

Verified benefits

Parental leave

12 weeks source

Non-birth-parent leave

12 weeks

Verified

Yes last checked unknown

Salary

$164K-$164K

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

147% above the BLS national median for design aggregate.

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Senior Semiconductor Design Engineer San Jose, CA Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in

Read the full description at micron.wd1.myworkdayjobs.com. FewerJobs shows a short excerpt and links to the source.