Senior Physical Design Integration Engineer
Intel - 2 Locations
Posted Apr 22, 2026
Verified benefits
- Parental leave
- 12 weeks source
- Non-birth-parent leave
- 12 weeks
- Verified
- Yes last checked unknown
- Salary
- Not disclosed
Market context
- Median wage (BLS OEWS)
- $66,396 national median
- Projected growth (BLS Employment Projections)
- +3.5% - Average
Matched to SOC 27-1024 - Design aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Where they hire
State eligibility is not yet verified.
About this role
Senior Physical Design Integration Engineer 2 Locations Senior Physical Design Integration Engineer /job/US-California-Folsom/Senior-Physical-Design-Integration-Engineer_JR0281584 2 Locations Posted 14 Days Ago
Read the full description at intel.wd1.myworkdayjobs.com. FewerJobs shows a short excerpt and links to the source.
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