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Silicon Design Verification Engineer, Quantum AI

Google - Mountain View, CA, USA; +1 more

Posted Jun 5, 2026

Benefits

Parental leave
18 weeks From the posting source checked Jun 20, 2026
Non-birth-parent leave
18 weeks From the posting source checked Jun 20, 2026
Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
Not verified
Relocation assistance
Not verified
Childcare support
Not verified
Learning budget
Not verified
Verification
Source-linked checked May 7, 2026
Salary
$138K-$198K From the posting source checked Jun 20, 2026
401(k) match
Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

44% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
Not verified
Weekend work
Not verified

Company

Company stage
Public-company From the posting source checked Jun 20, 2026
Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
Not verified
Assessment
Not verified
Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

Silicon Design Verification Engineer, Quantum AI Mountain View, CA, USA; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be a vital member of the quantum electronics team, providing key technical contributions in the area of ASIC design verification (DV) as we realize sophisticated electronics for control and readout of our future quantum computers. You will work as part of a team of digital, DV, physical design, and radio frequency/analog/mixed-signal engineers, collaborating with adjacent teams in the electronic, software, and quantum engineering areas to implement complex ASICs for use in the readout and control of our scaled quantum processors. As a Silicon DV Engineer, you will help drive the DV of all of Quantum's control and readout electronics. You will contribute to the entire verification lifecycle for our ASICs, collaborating with ASIC architects, digital designers to understand the chip functional requirements, plan out verification plans, and drive execution of those plans in collaboration with other DV engineers. You will build out and track coverage metrics to ensure thorough verification of designs. You will also work with external IP vendors, overseeing the DV work that they directly provide on their own IP and collaborating with these vendors to create suitable DV integration coverage. The full potential

Read the full description at www.google.com. FewerJobs shows a preview and links to the original posting.

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