Front-End CAD and IP Management Engineer, Silicon

Benefits

Parental leave

18 weeks Source: https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/. source Last checked May 7, 2026.

Non-birth-parent leave

18 weeks Source: https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/. source Last checked May 7, 2026.

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Source-linked checked May 7, 2026

Salary

$163K-$237K not verified - source not recorded; timestamp not recorded

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

Was this benefit information wrong? Tell us.

Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

79% above the BLS role benchmark for data and ml aggregate.

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

Not verified

Weekend work

Not verified

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Front-End CAD and IP Management Engineer, Silicon Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will serve as the critical link between IP development and SoC integration. You will be responsible for defining and executing the qualification standards that ensure third-party and internal IPs are ready for high-performance silicon designs. You will be developing automated front-end CAD flows, managing complex EDA tool collaterals, and collaborating with cross-functional teams to resolve technical integration bottlenecks. By streamlining the delivery process through advanced scripting and dashboarding, you will directly enable the team to hit dynamic tape-out schedules with high-quality, reliable silicon. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Lead the delivery of Silicon Internet Protocol (IP) to design teams to

Read the full description at www.google.com. FewerJobs shows a preview and links to the original posting.