Senior FPGA Engineer

Verified benefits

Parental leave

10 weeks source

Non-birth-parent leave

10 weeks

Verified

Yes last checked 2026-05-07

Salary

Not disclosed

Market context

Median wage (BLS OEWS)

$116,543 national median

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Senior FPGA Engineer Stafford Job Description Summary The Senior FPGA Development Engineer will be working to define requirements, implementation and enhance product features for world-class Control & Protection system in

Read the full description at gevernova.wd5.myworkdayjobs.com. FewerJobs shows a short excerpt and links to the source.