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Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions

General Dynamics - Scottsdale, AZ, US

Posted Jun 10, 2026

Benefits

Parental leave
Not verified
Non-birth-parent leave
Not verified
Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
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Relocation assistance
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Childcare support
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Learning budget
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Verification
Not verified checked Jun 13, 2026
Salary
Not verified
401(k) match
Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
Not verified
Weekend work
Not verified

Company

Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
Not verified
Assessment
Not verified
Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions Scottsdale, AZ, US Basic Qualifications Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience. CLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position What You'll Do Take ownership, lead, develop and maintain UVM-based and non-UVM-based verification environments for complex FPGA designs including cryptographic engines, protocol interfaces, and system-level integration testbenches Create comprehensive verification plans with functional coverage models, coverage goals, and closure criteria aligned to design specifications Implement constrained-random stimulus generators, monitors, scoreboards, and functional coverage collectors using SystemVerilog, VHDL and UVM Drive code coverage (statement, branch, condition, expression, toggle) and functional coverage to closure, analyzing coverage holes and developing targeted stimulus to fill gaps Develop and maintain automated simulation regression suites that run across multiple test configurations and random seeds Build and improve CI/CD pipelines for automated

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