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SI/PI Intern

Etched - San Jose, CA, United States

Posted Jun 10, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
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Mental health support
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Relocation assistance
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401(k) match
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Role

Role function
Security From the posting source checked Jun 20, 2026
Seniority
Entry From the posting source checked Jun 20, 2026

Schedule

Shift type
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Weekend work
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Company

Company stage
Growth-stage From the posting source checked Jun 20, 2026

Application

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Deadline
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About this role

SI/PI Intern San Jose, CA, United States About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary As a Signal Integrity / Power Integrity Intern, you will help design and validate the next generation of high-performance AI systems. You will work closely with package, PCB, ASIC, and system engineers to analyze high-speed interfaces, extract channel models, and improve signal quality across our accelerator platforms. This role provides hands-on experience with industry-leading tools and real-world challenges involving PCIe, Ethernet, high-speed SerDes channels, advanced packaging, and multi-board systems. Key Responsibilities - Signal Integrity Analysis - Perform channel analysis for high-speed interfaces including PCIe, Ethernet, and other SerDes links.Extract and validate S-parameter models from package and PCB layouts.Analyze insertion loss, return loss, impedance discontinuities, and crosstalk.Generate channel compliance reports and support design reviews.Modeling & Simulation - Build and validate 3D electromagnetic models using Ansys HFSS.Develop board and package channel models from ECAD design databases.Correlate simulation results with measurements and lab data.Support mixed package-board channel simulations and optimization.Design Collaboration - Partner with PCB layout, package, hardware, and ASIC teams to improve

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