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Power Validation Engineer

Etched - San Jose, CA, United States

Posted Apr 30, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
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  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
Offered From the posting source checked Jun 20, 2026
Relocation assistance
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Childcare support
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Learning budget
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401(k) match
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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
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Weekend work
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Application

Cover letter
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Assessment
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Deadline
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Where they hire

State eligibility is not yet verified.

About this role

Power Validation Engineer San Jose, CA, United States About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are looking for a Power Validation Engineer to own the end-to-end power characterization of our ASIC and the mezzanine card platform - from early silicon bring-up through production qualification. You will design measurement methodology, build test benches, and drive findings directly into silicon, package, and system design decisions. Key Responsibilities - Design and execute power measurement campaigns across all voltage rails (VDD_CORE, HBM, PCIe, AUX, etc) under realistic LLM inference and power virus workloads; characterize peak, sustained, and idle power envelopes across PVT corners and define derating curves used in system thermal and PDN specs - Validate power delivery network (PDN) performance - VRM load step response, PCIe power compliance, PDN impedance - and translate measurements into actionable feedback on capacitor placement, plane geometry, and de-cap strategy for PCB and package design teams - Profile power transient events (ramp rates, droop amplitudes, recovery profiles) and correlate them with on-die performance monitor data; build automated power sweep frameworks exercising

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