System Power Engineer, Principal

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

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Salary

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401(k) match

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Principal From the posting source checked Jun 20, 2026

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

System Power Engineer, Principal Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. System Power Engineer, Principal Location: Santa Clara, CA (Hybrid) Team: Hardware Engineering / Power Architecture About the Role As the Principal System Power Engineer , you will be the lead architect for the energy backbone of our AI accelerators. This role is unique in its breadth, spanning from the MCM (Multi-Chip Module)/Chiplet-level power distribution through the PCBA and into the system-level power shelf. You will solve the formidable challenge of delivering thousands of amps to high-performance silicon while maintaining razor-sharp power integrity. You aren't just managing power; you are engineering the efficiency and stability that makes large-scale AI inference possible. Key Responsibilities - Power Architecture & Design: Architect end-to-end power delivery solutions for high-TDP AI accelerators, focusing on multi-phase VRMs (Voltage Regulator Modules) and Point-of-Load (PoL) converters. - MCM & Chiplet Power Delivery: Lead the definition of power delivery for chiplet-based architectures, including

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