PCB Design Engineer, Sr Staff
d-Matrix - Santa Clara, Santa Clara, Ca, Ca, United States
Posted Apr 22, 2026
Benefits
- Parental leave
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- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- 401(k) match
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Schedule
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- Weekend work
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Application
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Where they hire
State eligibility is not yet verified.
About this role
PCB Design Engineer, Sr Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Sr. Staff PCB Layout Design Engineer Location: Santa Clara, CA (Hybrid/On-site) About the Role As a Sr. Staff PCB Layout Design Engineer , you will be the lead architect of the physical medium that connects our breakthrough AI silicon to the world. At d-Matrix, our "Corsair" platforms push the boundaries of signal density and power delivery. You will own the layout of high-complexity, high-layer-count PCBAs (20+ layers), ensuring that 112G/224G SerDes signals remain pristine and that thousands of Amps are delivered across the board with minimal loss. In this senior leadership role, you will also serve as the custodian of our Design Methodology , driving the automation, tooling, and rigorous constraint management processes that allow us to scale our hardware development with high precision and speed. Key Responsibilities • Full-Cycle System Layout: Lead the layout for high-complexity AI accelerator cards (PCIe form
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