Software Engineering Technical Leader, Control Systems - Acacia (Onsite)

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$164K-$235K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

71% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Work mode

Onsite From the posting source checked Jun 20, 2026

In-office days

5 days From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

May 15, 2026 From the posting source checked Jun 20, 2026

Where they hire

State eligibility is not yet verified.

About this role

Software Engineering Technical Leader, Control Systems - Acacia (Onsite) Maynard, Massachusetts, US The application window is expected to close on: 05/15/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This position is required to be onsite in Maynard, MA and in office three days a week. Meet the Team Acacia (part of Cisco) is a market leader in high-speed coherent optical transceivers, pioneering the development of coherent pluggable transceivers. Acacia's coherent products are deployed by all hyperscalers to connect their Data Centers over distances from a few kilometers to thousands of kilometers and even in submarine networks. The emergence of AI has drastically increased the demand for Acacia's coherent transceivers. Acacia's coherent transceivers are also being used in space applications and is eventually expected to be used inside data centers as interconnect speeds continue to increase. Acacia is also entering the PAM4 Client market and is expected to be a key provider of PAM4 solutions, including a 1.6T PAM4 DSP. Your Impact You will be a key member of Acacia's Software team responsible for embedded CPU code development to configure and manage our products. You will lead the architecture and design of complex optical sub-systems that go into future Acacia SOCs; collaborate with Chip, DSP and Optics architects to drive innovation in Acacia's products. You will interface with the wider cross-functional engineering team to architect the system software, develop algorithms, contribute to code development, and participate in

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