Physical Design Group Leader

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

Not verified

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

Was this benefit information wrong? Tell us.

Market context

U.S. role benchmark (BLS OEWS)

$66,396 U.S. median for this role

Projected growth (BLS Employment Projections)

+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Design From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Physical Design Group Leader 2 Locations Cisco Silicon One is seeking a Physical Design Group Leader. Meet the Team Physical Design team within Cisco Silicon One is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs. We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility. Your Impact You'll be part of the Cisco Silicon One team, which is at the heart of Cisco's software and ASIC design efforts. As the Physical Design Group Leader, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning. Minimum Qualifications · A VLSI Design with extensive experience in backend design · B.Sc./M.Sc. in Electrical Engineering. · Strong understanding of Place & Route flow. · 10+ years of hands-on experience in a relevant domain · 4+ years of proven Management or Technical Leadership experience. Preferred Qualifications · Deep understanding of all aspects of Physical construction and Integration. · Knowledge in Physical Design Verification methodology LVS/DRC. · Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). #li-as6 Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.