Chip Level STA Engineer

Verified benefits

Parental leave

13 weeks source

Non-birth-parent leave

13 weeks

Verified

Yes last checked unknown

Salary

Not disclosed

Where they hire

State eligibility is not yet verified.

About this role

Chip Level STA Engineer Armenia Meet the Team Join Cisco’s ASIC Physical Design Team, where we ensure the highest quality in full-chip timing closure and circuit performance to guarantee a

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a short excerpt and links to the source.