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ASIC/SoC Physical Design Engineer - Python/Perl/TCL/Shell Scripts - 7 to 12 years - Bangalore

Cisco - Pune, India

Posted Jun 7, 2026

Benefits

Parental leave
Not verified
Non-birth-parent leave
Not verified
Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
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Relocation assistance
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Childcare support
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Learning budget
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Verification
Not verified checked Jun 13, 2026
Salary
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401(k) match
Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
Not verified
Weekend work
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Company

Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
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Assessment
Not verified
Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC/SoC Physical Design Engineer - Python/Perl/TCL/Shell Scripts - 7 to 12 years - Bangalore Pune, India Meet the Team Cisco's Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG's ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry. You will work with Cisco's best-in-class Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures. We are looking for a talented and experienced Design Verification Lead to join our team and drive verification of Cisco's silicon photonics driver integrated circuits for the next generation of products for 100/200/400G per Lambda solutions. Your Impact Assist in RTL/netlist‑to‑GDSII implementation for block‑level and full‑chip designs in advanced technology nodes. Support digital implementation flows and collaborate with EDA tool vendors to debug issues. Support in developing hierarchical floorplans, macro placement, I/O planning, congestion, timing, and power distribution. Perform static timing analysis (STA), analyze timing reports, and implement timing

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Apply link verified; last checked Aug 3, 2026.

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