ASIC Engineer Part time Internship (1 year):

Benefits

Parental leave

Not verified

Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Engineer Part time Internship (1 year): Cairo Al Qahirah, Egypt Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. ASIC Engineer Part time Internship (1 year): Join the Cisco Common ASIC Group, a team responsible for developing the ASICs at the heart of Cisco's next-generation switching systems. These ASICs are becoming more general and programmable, moving beyond traditional high-speed packet forwarding. You will work with Cisco's outstanding switching solution team, driving the integration of Nexus systems and ACI with software like OpenStack, Docker, and Open vSwitch, to empower our customers in building multi-tenant clouds. Every time you access the Internet, chances are, your data has passed through one of our switches. You impact: Assist in the development and maintenance of advanced test benches and verification environments using System Verilog and UVM. Participate in the end-to-end verification process of complex ASIC design blocks. Help create comprehensive test plans and coverage points to ensure robust verification. Support the upgrade and refinement of test benches to integrate new features seamlessly. Collaborate with cross-functional teams for thorough cross-block verification and top-level integration. Minimum qualification Currently in your final year pursuing a Bachelor's or Master's degree in Electrical & Electronics Engineering (EE) or Computer Engineering (CE). Strong knowledge in Digital Design and ASIC flow. Familiarity with System Verilog-based verification Familiarity with UVM. Preferred

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