Senior Physical Design Engineer

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About this role

Senior Physical Design Engineer Singapore Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About the Role We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5nm, 3nm technology node. In this role, you will take ownership of physical implementation from RTL to GDSII, ensure timing and power closure for ultra-high-speed designs, and collaborate closely with cross-functional teams to resolve challenges unique to advanced nodes and multi-gigabit transceiver architectures. Key Responsibilities - Perform full-chip and block-level physical implementation including floor planning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in TSMC 3nm. - Collaborate with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power. - Work on advanced physical design techniques to support multiple voltage/frequency domains, hierarchical design, and physical-aware synthesis. - Handle advanced physical design topics: - EM/IR analysis and power grid optimization - Congestion analysis and mitigation - Clock domain crossing and

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