Senior Digital Design Engineer (AI Fabric)

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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Market context

Median wage (BLS OEWS)

$111,944 national median

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

59% above the BLS national median for data and ml aggregate.

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

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Weekend work

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Application

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Deadline

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About this role

Senior Digital Design Engineer (AI Fabric) San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview Join our team as Senior Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment. Key Responsibilities - Own the RTL implementation of complex digital designs from micro-architecture through sign-off. - Collaborate with verification teams to review test plans and debug issues. - Support efforts to achieve timing closure and implement Design-for-Test (DFT) features. - Scripting and automation for ASIC methodology improvement. - Accountable for quality and overall design success with the support of senior engineers. Required Qualifications Education & Experience: - Bachelor's degree in electrical engineering or equivalent - 3-8 years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets Digital Design Expertise: - Expertise in RTL coding with SystemVerilog

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