SIPI Architect for High-Speed SerDes

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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Mental health support

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Verification

Not verified last checked Jun 13, 2026

Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Market context

Median wage (BLS OEWS)

$116,543 national median

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

176% above the BLS national median for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

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Weekend work

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Application

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Deadline

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About this role

SIPI Architect for High-Speed SerDes San Francisco Bay Area, United States of America In this position, you will work with the team that develops SoCs. In this high-impact role, you will define and own the end-to-end signal and power integrity strategy for cutting-edge high speed SerDes. You will be responsible for ensuring robust interconnect performance from silicon to system. This position requires deep expertise in leading-edge SerDes technologies (224G+), modern interconnect protocols, and system-level co-design. As the SIPI Architect, you will define and own the end-to-end signal and power integrity architecture for high-speed SerDes interconnects. You will guide technical direction across various teams, lead system-level trade-off analyses, and ensure design robustness through advanced modeling and validation. Define and own the end-to-end SIPI (Signal and Power Integrity) architecture and strategy for cutting-edge high-speed SerDes links. Drive the technical direction and build consensus across cross-functional teams, including circuit design, packaging, system hardware, and validation, to deliver robust interconnect solutions. Lead system-level trade-off analysis to optimize interconnect performance, power, and cost across silicon, package, and system levels. Influence Apple's technology roadmap by providing expert guidance on future interconnect technologies, advanced packaging, and system-level co-design. Ensure robust interconnect design and performance by overseeing comprehensive modeling, simulation (statistical and time-domain), and silicon correlation. Develop and champion next-generation SIPI methodologies and best practices to guide design and analysis. Minimum Qualifications: BS and 20 +years of relevant industry experience. Preferred Qualifications: MS or PhD in Electrical Engineering or a related field with 20+ years of relevant industry

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