RF SoC Architect
Apple - Sunnyvale, United States of America
Posted May 8, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified not verified - source not recorded; timestamp not recorded
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
RF SoC Architect Sunnyvale, United States of America Do you have a passion for building innovative HW/SW for controlling modern RF transceivers? Do you enjoy hands-on, cradle-to-grave experience for building state-of-the-art cellular SoCs? In this role, you will have the opportunity to engage in architecture stages, and work with various teams to design, implement, verify, validate, bring-up, and productize advanced transceiver architectures. As part of an elite RF architecture team, you will define HW and FW control systems for real-time control, transceiver calibration, and more. Join us and help to innovate new wireless systems technologies that continually outperform the expectations! As part of an elite RF microarchitecture team, you will architect HW and FW sub systems for real-time mission mode operation, online calibrations, power management, and more. You will closely collaborate with design and verification teams, RF and cellular systems teams, RFFW and RFSW teams, and system validation and compliance teams to define, design, implement, and bring up wireless systems that deliver best-in-class user experiences. Define, develop, and author microarchitecture specifications for cellular SoCs consisting of CPUs, accelerators, fabric, memory, peripherals, and interfaces. Map system and algorithm requirements to HW/FW partitions to ensure state-of-the-art design covering all aspects of the system including functionality and performance. Ensure IP blocks and the SoC meet and exceed functional, performance, latency, debug-ability requirements within power and area constraints. Develop simulation models to accurately capture architecture functionality, analog, digital, and FW interfaces, Play a critical role in pre- and post-silicon verification, validation, and assist in
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