GPU Physical Design Engineer, STA/Timing

Benefits

Parental leave

Not verified

Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

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Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

GPU Physical Design Engineer, STA/Timing Austin, United States of America Do you love creating elegant solutions to sophisticated challenges? As part of our Silicon Engineering group, you'll help design and manufacture our next-generation, high-performance, power-efficient processors! You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. In this job, you will be responsible for timing closure of highly complex GPU designs that go in every Apple product and will have amazing opportunities to set new standards for the next generation GPU designs. You will gain exposure to different aspects of product development, from concept to post silicon validation! You will collaborate with a variety of fields including Architecture, RTL, Synthesis, Clocking, DFT, Physical design and Post silicon engineering to ensure the best design practices are followed for a smooth timing convergence. In this role you will: - Interact with RTL, architecture teams to understand physical design constraints related to timing and be the central point of contact to provide these to backend design flows. - Partner with Synthesis and Physical Design teams to implement the best design optimized for power, performance and timing. - Setting up all DFT modes and making sure all test features are properly timed. - Assemble the top level design for STA ensuring accurate analysis by reviewing all the logs and reports. - Create and maintain scripts and automation to ensure high quality STA reports and work with other teams for timing closure. - Run ECO flows

Read the full description at jobs.apple.com. FewerJobs shows a preview and links to the original posting.