Gate-level SigEM/SEB/FIT CAD Engineer

Benefits

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Family-building benefits

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Verification

Not verified last checked Jun 13, 2026

Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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About this role

Gate-level SigEM/SEB/FIT CAD Engineer Austin Metro Area, United States of America Imagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it! As a key member of our best-in-class CAD Group, you will be part of building innovative designs. We will apply your hands-on experience in electromigration (EM), static error band (SEB), failure in time (FIT), self-heating effect (SHE), and thermal analysis to develop, define, and refine the methodologies and flows for gate-level as well as transistor-level designs. Major tasks will include IP / SOC signal EM analysis for clock and data nets, SOC FIT budget validation, power-grid EM verification, 3DIC and interposer thermal integrity, power switch and standard cell EM/SHE characterization, design abstract and reuse, sign-off, and ECO, and much more. Are you ready to join some of the world's leading engineers, and help us deliver the next generation of ground-breaking Apple products? In this highly visible role, your primary responsibilities will include: • Contribute to the development and deployment of comprehensive EM/SEB/thermal methodologies across multiple advanced node designs • Develop and implement customized EM/SEB/thermal solutions

Read the full description at jobs.apple.com. FewerJobs shows a source-linked preview and links to the original posting.