CPU Physical Design Methodology and Optimization Engineer
Apple - Santa Clara, United States of America
Posted Apr 14, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
- Not verified
- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
- Not verified
- Relocation assistance
- Not verified
- Childcare support
- Not verified
- Learning budget
- Not verified
- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified not verified - source not recorded; timestamp not recorded
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
CPU Physical Design Methodology and Optimization Engineer Santa Clara, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! In this highly visible role as a part of an industry-recognized and innovative CPU design team; you will contribute to solving intriguing and key problems in the physical design (PD) methodology and optimization space. With a steadfast focus on improving Power, Performance and Area (PPA) of our industry leading CPU designs, you'll have the opportunity to work with most teams in CPU design and influence SOC teams as well. You will also be actively contributing to new and exciting technical areas including applying machine learning techniques in the silicon design space. • Work with CPU, CAD, and design teams to engineer new flows/algorithms to improve PPA • Detailed analysis across partitions to understand optimization opportunity • Develop new PD focused flows to improve CPU performance and efficiency • Cross-functional collaboration across STA, library, tech and post silicon team to
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