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CPU Debug and Power Management Verification Engineer

Apple - Beaverton, United States of America

Posted Apr 21, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
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Mental health support
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Relocation assistance
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Childcare support
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Learning budget
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Verification
Not verified last checked Jun 13, 2026
Salary
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401(k) match
Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Schedule

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Weekend work
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Application

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Deadline
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Where they hire

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About this role

CPU Debug and Power Management Verification Engineer Beaverton, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a chip design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly. We are seeking a highly motivated Design Verification Engineer to join our silicon engineering team focused on the auxiliary features of a high-performance ARM-based CPU. These features include Power Management, Clock Control, Debug Infrastructure, Resets, and Special-Purpose Registers-spanning both ARM-standard capabilities and Apple-specific innovations. • You will work across the entire product lifecycle, from pre-silicon test planning to supporting post-silicon bring-up and debug when needed. This role is highly cross-functional, bridging CPU and SoC teams, and is critical to delivering robust, low-power, high-performance CPU designs. • Work closely with architecture and RTL designers on verifying the functionality

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