Sr. RFIC PLL Design Engineer , Amazon Leo
Amazon - San Diego, California, USA
Posted May 5, 2026
Benefits
- Parental leave
- 6 weeks From the posting source checked Jun 20, 2026
- Non-birth-parent leave
- 6 weeks From the posting source checked Jun 20, 2026
- Family-building benefits
- Mental health support
- Offered From the posting source checked Jun 20, 2026
- Relocation assistance
- Not verified
- Childcare support
- Offered From the posting source checked Jun 20, 2026
- Learning budget
- Not verified
- Verification
- Source-linked checked Jun 7, 2026
- Salary
- $159K-$215K From the posting source checked Jun 20, 2026
- 401(k) match
- Reported from DOL Form 5500 industry filing (not employer-specific)
Was this benefit information wrong? Tell us.
Market context
- U.S. role benchmark (BLS OEWS)
- $116,543 U.S. median for this role
- Projected growth (BLS Employment Projections)
- +9.8% - Much faster than average
61% above the BLS role benchmark for software engineering aggregate.
Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Role
Schedule
- Shift type
- Not verified
- Weekend work
- Not verified
Company
- Equity
- Offered Verified - SEC 10-K source checked Jun 20, 2026
Application
- Cover letter
- Not verified
- Assessment
- Not verified
- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Sr. RFIC PLL Design Engineer , Amazon Leo San Diego, California, USA Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. Come work at Amazon! The Role: As Senior RFIC PLL Design Engineer, you will engage with an experienced cross-disciplinary staff to conceive and design innovative product solutions. You will work closely with an internal inter-disciplinary team, and third party suppliers to drive key aspects of product definition, execution and optimization. You must be responsive, flexible and able to succeed within an open collaborative peer environment. As a member of the RFIC team, you will be responsible for the architectural definition, design, simulation, layout, and extracted simulation for RF and clock PLLs (including frac-N) as well as transmit and receive front-ends from data converters to LNAs and PAs. This position requires strong knowledge of PLL design, especially for mmWave circuits. Strong focus will be on creating power and cost optimized solutions for a given system performance. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Key job responsibilities • Collaborate with communications systems, digital design, and chip implementation teams to specify and implement transceivers and RFIC front-end models which will delight future Amazon LEO customers. • Lead implementation of area/power-efficient
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