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Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs

Amazon - Cupertino, California, USA

Posted Mar 16, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
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Market context

Median wage (BLS OEWS)
$111,944 national median
Projected growth (BLS Employment Projections)
+13.7% - Much faster than average

92% above the BLS national median for data and ml aggregate.

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

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Weekend work
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Application

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About this role

Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs Cupertino, California, USA Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Amazon Web Services (AWS) is the world's most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating - that's why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses. Key job responsibilities - As a key member of the ASIC design team, you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications. - Integrate multiple subsystems into top level SOC,

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