Senior Digital ATE Test Engineer, Amazon Leo Silicon Team
Amazon - Sunnyvale, California, USA
Posted May 20, 2026
Benefits
- Parental leave
- 6 weeks From the posting source checked Jun 20, 2026
- Non-birth-parent leave
- 6 weeks From the posting source checked Jun 20, 2026
- Family-building benefits
- Mental health support
- Offered From the posting source checked Jun 20, 2026
- Relocation assistance
- Not verified
- Childcare support
- Offered From the posting source checked Jun 20, 2026
- Learning budget
- Not verified
- Verification
- Source-linked checked Jun 7, 2026
- Salary
- $183K-$248K From the posting source checked Jun 20, 2026
- 401(k) match
- Reported from DOL Form 5500 industry filing (not employer-specific)
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Market context
- U.S. role benchmark (BLS OEWS)
- $116,543 U.S. median for this role
- Projected growth (BLS Employment Projections)
- +9.8% - Much faster than average
85% above the BLS role benchmark for software engineering aggregate.
Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Role
Schedule
- Shift type
- Not verified
- Weekend work
- Not verified
Company
Application
- Cover letter
- Not verified
- Assessment
- Not verified
- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Senior Digital ATE Test Engineer, Amazon Leo Silicon Team Sunnyvale, California, USA Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. As a Senior Digital ATE Test Engineer, you will be a key contributor to the development and execution of high-volume production test solutions for custom modem and communication SoCs powering Amazon Leo's satellite constellation. You will partner closely with DFT, ASIC design, and manufacturing teams to translate design-for-test content into production-ready test programs from initial pattern conversion and silicon bring-up through high-volume manufacturing release. This role demands deep expertise in digital ATE test methodology for complex modem/communication processors, with a strong emphasis on pattern conversion workflows (STIL/WGL to ATE-native formats), production test program bring-up, high-speed I/O and SERDES characterization and production testing, and tight collaboration with DFT teams to ensure comprehensive fault coverage and test quality. You must be responsive, flexible, and able to succeed within an open, collaborative, cross-functional environment. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Key job responsibilities - Develop and own production test programs for complex digital/modem SoCs on Teradyne UltraFLEX and Advantest platforms, from initial bring-up through high-volume manufacturing release. - Lead pattern conversion efforts: translate DFT-generated patterns (STIL/WGL) into tester-executable formats
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