Pre-Silicon SoC Modeling Engineer, Annapurna Labs Machine Learning Accelerators, AWS

Benefits

Parental leave

6 weeks From the posting source checked Jun 20, 2026

Non-birth-parent leave

6 weeks From the posting source checked Jun 20, 2026

Family-building benefits

• Fertility benefits: Offered From the posting source checked Jun 20, 2026
• Adoption assistance: Offered From the posting source checked Jun 20, 2026
• Surrogacy assistance: Offered From the posting source checked Jun 20, 2026

Mental health support

Offered From the posting source checked Jun 20, 2026

Relocation assistance

Not verified

Childcare support

Offered From the posting source checked Jun 20, 2026

Learning budget

Not verified

Verification

Source-linked checked Jun 7, 2026

Salary

$165K-$224K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

67% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Pre-Silicon SoC Modeling Engineer, Annapurna Labs Machine Learning Accelerators, AWS Cupertino, California, USA AWS's Trainium and Inferentia chips power the world's largest machine learning clusters. Our team builds C++ models of these custom SoCs that RTL designers, verification engineers, and software teams depend on throughout the silicon development lifecycle. We're looking for a modeling engineer to build and own models that directly impact how our chips are designed, verified, and brought to production. What you'll do: - Build and own models of SoC subsystems - translating architecture specs and RTL behavior into accurate, testable C++ models - Work directly with RTL design and verification teams to validate model behavior against RTL, debug discrepancies, and support pre-silicon verification flows - Develop model-based test infrastructure: regression suites, RTL correlation checks, and coverage-driven testing - Contribute to performance modeling efforts - building cycle-approximate models that help architects evaluate design trade-offs before RTL exists - Improve modeling methodology and infrastructure: how models are structured, integrated, tested, and released to DV and architecture teams - Collaborate with chip architects to understand upcoming designs and plan modeling work ahead of RTL availability Why this role is interesting: - Your models are used to verify silicon before it's built - bugs you catch save months of schedule and millions of dollars - You'll work at the intersection of software engineering and chip design, with deep visibility into how custom ML accelerators are architected - As the team scales, there's a clear path into architectural modeling - using

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