PD Engineer, Annapurna Labs

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

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Salary

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401(k) match

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Market context

Median wage (BLS OEWS)

$111,944 national median

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

65% above the BLS national median for data and ml aggregate.

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

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Where they hire

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About this role

PD Engineer, Annapurna Labs Cupertino, California, USA As a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of Hardware in our data centers including technologies such as AWS Inferentia which is a machine learning inference product designed to deliver high performance at low cost. You'll provide leadership in the application of new technologies to large scale deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you'll work with thought-leaders in multiple technology areas. You'll have relentlessly high standards for yourself and everyone you work with, and you'll be constantly looking for ways to improve our products' performance, quality and cost. We're changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today. Key job responsibilities - Drive block physical implementation through synthesis, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off - Develop cloud infrastructure to support physical design work. - Drive improvement in RTL2GDS flows/methodology for PPA and TAT improvement. - Create Dashboard/central reports for project tracking and visualizing QoR/stats - Interface directly with RTL, Package Design, DFT and other teams to improve methodologies and efficiencies and drive efforts to resolution. - Work with EDA tool vendors to evaluate new tools, solve bugs, improve usability, etc. Basic Qualifications: - Bachelor's degree in Electrical Engineering or a

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