EMIR Engineer, Annapurna Labs - Cloud Scale Machine Learning
Amazon - Cupertino, California, USA
Posted May 13, 2026
Benefits
- Parental leave
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- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
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- Salary
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- 401(k) match
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Schedule
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
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Where they hire
State eligibility is not yet verified.
About this role
EMIR Engineer, Annapurna Labs - Cloud Scale Machine Learning Cupertino, California, USA Our Machine Learning Acceleration (MLA) team develops the Inferentia and Trainium SoCs that are used to power today's AI workloads in datacenters all around the world. As a Sr. SoC EMIR Engineer, you'll contribute to the EMIR sign-off of our SoCs and help maintain a high bar on quality. We're searching for an experienced EMIR engineer with a proven track record of handling challenges at scale. In this role, you'll be working directly with architects, designers, verification engineers, power integrity engineers and physical design experts - defining best practices in power grid design, developing test cases & vectors to model demand currents accurately, modeling & signing-off EMIR taking into account board and package impact, advancing the state-of-the-art in EMIR analysis and modeling. Key job responsibilities * Design & analyze power grids * Setup flows for EMIR analysis * Run EMIR analysis for large subsystems, SoCs * Partner with EDA tool vendors to develop / evaluate new methodologies for EMIR analysis * Develop and maintain dashboards for EMIR rollups * Work with designers, architects, Verification engineers and Physical Design engineers to develop vectors for IR analysis, Thermal analysis and power estimation A day in the life Depending on the state of the project, you may find yourself working on the following: * Design and evaluate power grids * Working with designers, architects and verification engineers to come up with worst-case vectors for power and IR analysis * Root cause
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