DFT Design Engineer, Machine Learning Acceleration

Benefits

Parental leave

6 weeks From the posting source checked Jun 20, 2026

Non-birth-parent leave

6 weeks From the posting source checked Jun 20, 2026

Family-building benefits

• Fertility benefits: Offered From the posting source checked Jun 20, 2026
• Adoption assistance: Offered From the posting source checked Jun 20, 2026
• Surrogacy assistance: Not verified

Mental health support

Offered From the posting source checked Jun 20, 2026

Relocation assistance

Not verified

Childcare support

Offered From the posting source checked Jun 20, 2026

Learning budget

Not verified

Verification

Source-linked checked Jun 7, 2026

Salary

$136K-$184K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

37% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not required From the posting source checked Jun 20, 2026

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

DFT Design Engineer, Machine Learning Acceleration Austin, Texas, USA Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team, you'll be responsible for designing and optimizing hardware in our data centers, including AWS Inferentia and Trainium systems-our custom-designed machine learning inference and training servers. Our success depends on world-class server infrastructure as we handle massive scale and rapidly integrate emerging technologies. We're looking for an ASIC DFT Design Engineer to help us trailblaze new technologies and architectures while ensuring high design quality and making the right trade-offs. Key job responsibilities • Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes • Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions • Perform RTL coding and Verification using Verilog/System Verilog • Utilize industry standard DFT tools to create high coverage and cost-effective test patterns to target advanced silicon defects • Participate in Silicon debug efforts alongside ATE and System teams • Communicate and work with team members across multiple disciplines Basic Qualifications: - Bachelor's degree in Electrical or Communications Engineering or a related field - 5+ years of practical DFT experience with complex SoC designs in advanced technology nodes - Experience with standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time - Experience with automation script development Preferred Qualifications: - Master's degree in Electrical or Communications Engineering

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